Efficient Hardware Implementation of Digital Filters using Distributed Arithmetic (DA)

The FPGA (Field Programmable Gate Array) constitute of many programmable modules like Configuration Logic Blocks (CLBs), Block Random Access Memories (BRAM), DSP 48 blocks and Input/output (I/O) modules. The CLBs are the main programmable logic units which consist of different number of logic slices and each slice contains different number of LUTs and flips flops depending upon the FPGA device family. The CLBs and DSP 48 blocks are the most expensive resources on the FPGA and are used wisely in the design of FPGA based system. In most of FPGA based DSP applications, CLB’s and DSP 48 blocks are utilized in implementing algorithmic logic and digital filters whereas the BRAM remains unutilized. The non utilization of FPGA resources like BRAM motivates to implement various DSP module like filters (FIR or IIR) using BRAM. The Distributed Arithmetic (DA) is a technique which can be used to implement digital FIR and IIR filters. The DA logic replaces the MAC operation of convolution summation of any digital filter (IIR or FIR) into a bit serial look up table read and addition operation. Hence by implementation of digital filters using DA, expansive FPGA resources like DSP 48 block can be saved and used to implement the algorithmic logic for DSP algorithms. The research paper presents an efficient method for hardware implementation of digital filters (IIR and FIR) of any order by exploiting Distributed Arithmetic (DA). This paper presents critical analysis and optimization provided by the purposed design with respect to its conventional DA based design.